This article investigates rising up throughput of partially parallel LDPC-decoder problem. The decoder uses irregular parity check matrix. Models of memory organization with double buffer for storing input message data and results of computations are provided. Possible cases of practical models implementation are considered. Proposed approaches allow to rise up throughput of decoder and can be used in decoder implementation for different types of matrix.
LDPC-decoder, double buffer organization
"Pidvyshchennia shvydkodii LDPC-dekoderu na osnovi orhanizatsii podviinoho buferu vkhidnoho povidomlennia" ,
Information Processing Systems,