The article describes the results of an experimental study ways to reduce the bit depth of the input code in the structure of the Moore FSM for the implementation in a CPLD basis. The studies derived formulas for estimating the required area CPLD chip, as well as the defined ratio relationship of practical use of macrocells and the theoretical amount of logic gates needed to implement the schemes of control of the automaton. The resulting ratio enables to assess in advance the cost of the project. Investigations were carried out on the basis of the control algorithm onboard digital computer complex.
control automaton, CPLD, pseudoequivalent state, hardware expenses, macrocell, control algorithm